1. Field of the Invention
This invention relates to a polishing apparatus and a method for planarizing a layer on a semiconductor wafer.
2. Description of the Related Art
Conventionally, colloidal silica is popularly used as a polishing slurry for polishing and planarizing the surface of insulating films or the like in the process of manufacturing semiconductor devices.
There are used colloidal silica granules of a diameter as large as tens of several nanometers. The granules are normally obtained by growing sodium silicate in water. Obtained granulous silica is then mixed with water to form a suspension or colloidal silica, to which KOH or NaOH is added to regulate the hydrogen ion concentration of the suspension and at the same time achieve an enhanced polishing efficiency for the slurry.
Compol-80 marketed by Fujimi Corporation is one of commercially available polishing slurries of the above described type containing an alkali metal. When a silicon oxide film is polished or scraped by using the slurry, the alkali metal contained in the slurry is at least partly dispersed into the silicon oxide film or the semiconductor device. When the device is a MOS device, the dispersed metal fluctuates the threshold voltage level of the device to significantly reduce the reliability of the semiconductor device.
In order to avoid this problem, some preventive measures need to be taken such as additionally forming a protective film layer under the silicon oxide film to block dispersion of alkali metal, making the overall process of manufacturing semiconductor devices rather cumbersome and complicated.
Now, how a prior art semiconductor device is produced will be briefly described by referring to illustrations showing its sectional views in various stages of preparation. FIG. 1A of the accompanying drawings illustrates a conventional semiconductor device comprising a semiconductor substrate 1 and electrode or wire patterns designated by reference numeral 2. To protect the patterns, a protective film 3 is firstly formed on the entire surface area of the semiconductor structure, and subsequently a resist 4 is applied onto the film 3 and then the resist 4 is subjected to a patterning operation by using a lithographic technique, as illustrated in FIG. 1B. Thereafter, the protective film 3 is selectively removed as the resist 4 is used as masks. Thereafter, the resist 4 is removed to produce a patterned protective film as shown in FIG. 1C. Thereafter, as illustrated in FIG. 1D, a silicon oxide film 5 is formed on the semiconductor structure, and then its surface is planarized using a polishing method to produce a planar surface, as shown in FIG. 1E. However, the above conventional method additionally requires the steps of FIGS. 1A through 1C, thus complicating the entire manufacturing process.
There is also used another polishing slurry of the colloidal silica series containing no alkali metal. The slurry is obtained by performing pyrolysis of silicic acid tetrachloride or hydrolysis of organic silane to grow silica particles, and regulating the hydrogen ion concentration of the produced silica by means of ammonia or an amine. This type of polishing slurry is, however, accompanied by a problem of an unpractically low polishing speed if used for silicon oxide films.
On the other hand, a well known method of polishing the surface of glass photo-masks comprises steps of primary polishing using a suspension of aluminum oxide and finish polishing using another suspension containing cerium oxide particles having an average particle size of several micrometers. However, such a two-step polishing operation involved in the process of manufacturing semiconductor devices is not recommendable by any means, considering the fact that an insulating film needs to be polished to reduce its thickness by only several micrometers. Furthermore, in the process of manufacturing semiconductor devices, an insulating film layer is often formed on the surface of a semiconductor substrate that carries raised portions (conductive layers) having a height of several hundreds to thousands nanometers. Such differences in height of the surface of a semiconductor device will be clearly reflected onto the profile of the insulating film formed thereon. The step configuration of the surface of the insulating film need to be planarized by polishing. However, it has not at all been known for sure if cerium oxide particles having an average size of several micrometers can successfully polish and planarize the surface that has a configuration of different heights of several hundreds to thousands nanometers and if the insulating film will be contaminated by the alkali metal as in the case where colloidal silica is used. All in all, the above described method of polishing the surface of a glass layer operating as a photo-mask has been developed without taking into consideration if it can be applied to the operation of polishing semiconductor devices during the manufacturing process.
The above conventional methods of polishing semiconductor devices, using colloidal silica or the like as a polishing slurry, are accompanied by the problem of contamination by alkali metal and that of a slow polishing rate.
While a method of using a suspension that does not contain cerium oxide particles is also known in the technology of polishing the surface of glass photo-masks, it is not certain at all if such a method can polish and planarize a surface having a profile of steps of several hundreds to thousands nanometers high and if it is not accompanied by a problem of metal contamination. Again, it is a method that has been developed without taking into consideration if it can be applied to the operation of polishing semiconductor devices during the manufacturing process.
Now, a typical known polishing and planarizing technique of the category under consideration will be described by referring to FIGS. 2A through 2C of the accompanying drawings. As illustrated in FIG. 2A, a semiconductor device is prepared by forming an SiO.sub.2 film 12 on an Si semiconductor device 1 and then a metal wires 13 having a thickness of 1.1 .mu.m are appropriately formed on the SiO.sub.2 film 12 to produce a given pattern of metal wires.
Thereafter, another SiO.sub.2 film 14 is formed on the entire surface of the above intermediate product. Consequently, the surface of the second SiO.sub.2 layer shows raised portions and recessed portions, reflecting the pattern of metal wires. Then, the surface of the second SiO.sub.2 layer 14 is polished to remove the raised and recessed portions. The operation of polishing or scraping the surface of the second SiO.sub.2 layer 14 will be carried out by using a polishing apparatus as illustrated in FIG. 3.
More specifically, an Si substrate 1 having a configuration as described above is set in position on the turntable the apparatus under a holder 501. A polishing slurry feed pipe 503 is disposed above the turntable 502 to feed a polishing slurry onto the truntable during the operation of polishing the substrate. A polishing cloth 504 is disposed between the surface to be polished of the Si substrate 1 and the turntable 502 so that the raised and recessed portions on the surface of the semiconductor substrate are removed by particles of the polishing slurry and the polishing cloth 504 to provide a planarized surface of the semiconductor substrate.
The holder 501 is subjected to a load of 40 kfg and rotated at a rate of 100 rpm. The turntable is rotated at the same rotation speed.
While the above described polishing method using a polishing apparatus can significantly reduce the raised portions on the surface of the second SiO.sub.2 film 14, it also dishes the portions of the second SiO.sub.2 film 14 that are located between adjacent metal wires 13. This is a phenomenon normally referred to as "dishing".
FIG. 4 is a graph showing the result of an analysis of the "dishing" phenomenon observed in a case where each of the metal wires 13 is 500 .mu.m wide and separated from any adjacent wires by 1,000 .mu.m. In the graph of FIG. 4, the abscissa represents the polishing time expressed in seconds, and the coordinate represents the distance between the surface of the first SiO.sub.2 film 12 and the that of the second SiO.sub.2 film 14.
Before starting the polishing operation, the distance (solid line in FIG. 4) between the areas (raised portions) of the surface of the SiO.sub.2 film 12 carrying a metal wire 13 and the surface of the SiO.sub.2 film 14 and the distance (broken line in FIG. 4) between the areas (recessed portions) of the surface of the SiO.sub.2 12 film carrying no metal wire and the surface of the SiO.sub.2 film 14 show a difference of 1.1 .mu.m which is equal to the height of the metal wires 43.
As the polishing operation proceeds, the difference between the distance separating the surface of the SiO.sub.2 film 12 and that of the SiO.sub.2 film 14 at the raised portions and the corresponding distance at the recessed portions is reduced because the speed at which the SiO.sub.2 film 14 is polished off for the raised portions is greater than the speed at which it is polished off for the recessed portions. The reason for the difference in speed is that the SiO.sub.2 film 14 is subjected to a greater load at the raised portions.
However, the rate at which the difference between the distance separating the surface of the SiO.sub.2 film 12 and that of the SiO.sub.2 film 14 at the raised portion and the corresponding distance at the recessed portions is reduced is actually very low. If the polishing operation is conducted for 70 seconds and the SiO.sub.2 film 14 is polished off by approximately 1.0 .mu.m at the raised portions, the thickness of the SiO.sub.2 film 14 will be reduced by approximately 0.65 .mu.m by polishing so that consequently there will remain a difference of approximately 0.35 .mu.m between the distance separating the surface of the SiO.sub.2 film 12 and that of the SiO.sub.2 film 14 at the raised portions and the corresponding distance at the recessed portions.
The surface of the SiO.sub.2 film 14 can be almost completely and satisfactorily planarized by forming a rather thick SiO.sub.2 film and polishing the film to a large extent.
Such a method of forming a thick film and polishing off the film is, however, very time consuming and hence increases the manufacturing cost. Moreover, the more the film is polished, the greater becomes the fluctuations in the polishing speed on the film, a phenomenon by no means favorable for the polishing operation.
The above described dishing phenomenon for the recessed portions can be prevented by forming, for instance, a silicon nitride film as a "polish stopper" for the recessed portions in order to suppress the rate of polishing the SiO.sub.2 film 14 at the recessed portions and increase the rate at which the difference in the thickness of the SiO.sub.2 film 14 at the raised and recessed portions is reduced.
This technique is schematically illustrated in FIGS. 5A through 5D, which show a semiconductor structure in cross section. Referring firstly to FIG. 5A, an SiO.sub.2 film 12 is formed on an Si substrate and (1.1 .mu.m thick) metal wires 13 are formed thereon in a manner as described before.
Thereafter, another SiO.sub.2 film 14 is formed on the entire surface of the intermediate product as shown in FIG. 5B.
Then, a silicon nitride film 15 is formed on the SiO.sub.2 film 14 and subsequently is subjected to a patterning operation, in which, as shown in FIG. 5C, the silicon nitride film 15 is removed except at the recessed portions where no metal wires are formed under the SiO.sub.2 film 14.
Finally, the surface of the SiO.sub.2 film 14 is polished by using a polishing apparatus as illustrated in FIG. 3 in a manner same as the one described above.
With this technique, the hight difference significantly disappears from the surface of the SiO.sub.2 film 14 as shown in FIG. 5D, and the dishing of the SiO.sub.2 film 14 is also reduced. However, the SiO.sub.2 film 14 shows slight upward bulges in areas of the metal wires 13 to provide small increased and recessed portions that are reversals of those of the SiO.sub.2 film 14 before the SiO.sub.2 film 14 is polished.
The result of an analysis looking into this phenomenon is summarized in FIG. 6. The object of the analysis is a device comprising metal wires 13 have a width of 500 .mu.m and arranged with a distance of 1,000 .mu.m separating adjacent wires. The abscissa of the graph of FIG. 6 represents the polishing time (seconds) in the processing step of FIG. 5D, while the coordinate represents the distance between the surface of the first SiO.sub.2 film 12 and the that of the second SiO.sub.2 film 14.
Before the start of the operation of polishing the device, the distance (solid line in FIG. 6) between the areas (raised portions) of the surface of the SiO.sub.2 film 12 carrying a metal wire 13 and the surface of the SiO.sub.2 film 14 and the distance (broken line in FIG. 6) between the areas (recessed portions) of the surface of the SiO.sub.2 12 film carrying no metal wire and the surface of the SiO.sub.2 film 14 show a difference of 1.1 .mu.m which is equal to the height of the metal wires 13.
As the polishing operation proceeds, the difference between the distance separating the surface of the SiO.sub.2 film 12 and that of the SiO.sub.2 film 14 at the raised portions and the corresponding distance at the recessed portions is reduced because the speed at which the SiO.sub.2 film 14 is polished off for the raised portions is greater than the speed at which it is polished off for the recessed portions. The reason for the difference in speed is that the SiO.sub.2 film 14 is subjected to a greater load at the raised portions. Additionally with this technique, the speed at which the SiO.sub.2 film 14 is polished is very low at the recessed portions when compared with the speed at which it is polished at the raised portions because of the silicon nitride films 15 formed on the recessed portions and consequently the difference between the distance separating the surface of the SiO.sub.2 film 12 and that of the SiO.sub.2 film 14 at the raised portions and the corresponding distance at the recessed portions is further reduced because the higher speed at which the SiO.sub.2 film 14 is polished off for the raised portions.
Approximately 70 seconds after the start of the polishing operation, the difference between the distance separating the surface of the SiO.sub.2 film 12 and that of the SiO.sub.2 film 14 at the raised portions and the corresponding distance at the recessed portions is reduced to almost nil to make the surface of the SiO.sub.2 film 14 flat. However, since the polishing operation is continued after the surface of the SiO.sub.2 film 14 has become flat, the areas of the surface of the SiO.sub.2 film 14 not covered by a silicon nitride film 15, or the original raised portions, are further polished to make the film even thinner.
Thus, the difference between the distance separating the surface of the SiO.sub.2 film 12 and that of the SiO.sub.2 film 14 at the raised portions becomes smaller than the corresponding distance at the recessed portions to provide small raised and recessed portions that are reversals of those of the SiO.sub.2 film 14 before the SiO.sub.2 film 14 is polished.
Such reversals of raised and recessed portions on the surface of the SiO.sub.2 film 14 can be prevented from occurring by optimizing the thickness of the silicon nitride film 15 in such a manner that it may disappear when the surface of the SiO.sub.2 film 14 is made completely flat. However, such a method of optimization of the silicon nitride film thickness will not be feasible for industrial applications, because of the narrow range of the optimum thickness. Furthermore, the formation of a stopper film, a silicon nitride film in particular, and the operation of patterning the film which are indispensable for the technique under consideration are rather complicated and involve a high additional cost.
Therefore, the known technique of using an insulating film as an aid to the operation of polishing and planarizing the surface of a semiconductor device is also accompanied by the phenomenon of "dishing" that appears on the recessed portions to make the operation quite unsatisfactory.
There has been proposed a technique to suppress the occurrence of "dishing" by selectively forming a stopper film, a silicon nitride film in particular, only on the recessed portions.
With this technique, however, "dishing" appears on the raised portions that carry no stopper film immediately after the insulating film is planarized so that again it is practically impossible to achieve a satisfactorily planar surface for the semiconductor device.
FIGS. 7A and 7B of the accompanying drawings illustrate the process of polishing and planarizing the surface of a semiconductor device by using still another known technique.
FIG. 7A shows a conventional semiconductor device comprising a semiconductor substrate 1 and a finely designed patterns 32 of various elements including multilayered wires, semiconductor polycrystalline layers, capacitors and electrodes realized in the form of a combination of fine projections selectively formed on the substrate 1. The patterns 32 are separated from one another by spaces, or recessed areas 33, 34, of which each of the recesses 33 represents a space separating two adjacent elements that are located close to each other whereas each of the recesses 34 separates two adjacent elements with a large distance. The semiconductor device further comprises an insulating film 35 formed to cover the pattern 32 and a resist layer 36 formed on the insulating film 35 by applying a resist material. Thus, the resist layer 36 has a varying thickness which is greater on the relatively wide recesses 34 than on the narrower recesses 33. Subsequently, this resist 36 is etched back to expose the insulating film 35 by, for instance, reactive ion etching (RIE) as illustrated in FIG. 7B, where 36a denotes those areas of the insulating film 35 located on the recesses 33 whereas 36b denotes the areas found on the recesses 34. As seen from FIG. 7B, the surface of the insulating film 35 is undulated because, as the etch back operation proceeds on the resist 36, the insulating film 35 comes to be quickly exposed and etched at locations above the recesses 33 where the resist 36 is relatively thin.
FIGS. 8A and 8B of the accompanying drawings illustrate the process of polishing and planarizing the surface of a semiconductor device by using still another known technique. This process is normally carried out before a multilayer structure is produced in the device.
Referring to FIG. 8A, the semiconductor device comprises a semiconductor substrate 1 and a polysilicon high melting point metal silicide layer 42 selectively formed as capacitors or electrodes on the semiconductor substrate 1 to provide a number of elements of the layer. Spaces defined by adjacent elements of the polysilicon high melting point metal silicide layer 42 provides so many recesses, of which those having a relatively small width are denoted by reference numeral 43, whereas reference numeral 44 denotes those recesses having a relatively layer width. The semiconductor device further comprises an insulating film 45 formed to cover the entire surface of the device, said insulating film 45 being typically made of boron phosphorous silicon glass (BPSG). When the BPSG film is caused to reflow by using a phosphor dispersion melt technique as illustrated in FIG. 8B, the BPSG film 45 comes to show a remarkably undulated surface which is higher at locations above the wider recesses 42 separating elements of the polysilicon high melting point metal silicide layer 42 than at locations above the narrower recessed 43 that also separates elements of the layer 42.
As may be understood from the above description, known techniques for polishing and planarizing the surface of a semiconductor device are, in most cases, required to deal with surface layers having a number of projections formed typically by electrodes, capacitors and wires and also with surface layers having a number of recesses produced normally by trenches and contact holes. The surface of a semiconductor device having such an uneven surface layer is then planarized by forming an insulating film thereon and etching the film back or causing the film to reflow.
However, the operation of etch back or reflow cannot satisfactorily planarize the surface of an insulating film because the recesses on the surface of a semiconductor device of the type under consideration have widely different widths. That is, the undulated surface of such an insulating film cannot be completely planarized.
Obviously, the undulations remaining on the insulation film of a semiconductor device can have disadvantages on the following steps in the manufacturing process.
Assume, for example, that a wiring material is laid on the surface of a semiconductor device having remaining undulations thereon and then subjected to a patterning operation. Then, rays of light emitted on the layer of the material for the patterning operation may not be accurately focused on the layer and the produced wiring may exhibit a disturbed pattern. In view of the recent trend of producing highly integrated devices requiring a precision level of submicrons and having a relatively large difference in the height between central and peripheral areas and a very narrowed space between any adjacent wires of the chip, such undulations on the surface can adversely affect not only the make of the patterned wiring but also the electric characteristics of the device.
Additionally, while the technique of RIE is popularly used for the etching back operation, it can give rise to a loading effect which is specific to anisotropic etching and attributable to the difference in the size of the openings and the pattern to space ratio of the device so that the rate and shape of etching may be adversely affected by that effect to degrade the controllability of the technique.
Thus, there have been observed problems of broken wires and sort circuits on semiconductor devices of the type under consideration that can significantly reduce the yield of manufacturing devices and reduces the reliability of produced devices.
FIGS. 9A through 9C of the accompanying drawings illustrate in cross section a known semiconductor device in three different steps of polishing and planarizing the insulating film.
Referring firstly to FIG. 9A, an SiO.sub.2 film 52 is formed in an Si semiconductor substrate 1 and thereafter a lower wiring layer 53 is formed on the SiO.sub.2 film 52.
Then, as shown in FIG. 9B, another SiO.sub.2 film 54 is formed by deposition to cover the entire surface of the semiconductor substrate 1 including the areas occupied by the lower wiring layer 53. Thereafter, the SiO.sub.2 film 54 is partly removed by polishing as shown in FIG. 9C.
The polishing operation is carried out to remove the undulations on the surface of the SiO.sub.2 film 54 as shown in FIG. 9B and make the surface flat.
However, as FIG. 9C suggests, while it is relatively easy to partly flatten the surface of the SiO.sub.2 film 54, the entire surface of the film 54 cannot be made completely planar without difficulty because the extent to which the SiO.sub.2 film 54 is polished off varies depending on the position on the Si substrate 1. It is also not an easy task to control the extent of polishing the film 54.
A conceivable method of controlling the extent of polishing the SiO.sub.2 film 54 is to form an additional layer of silicon nitride film and use the layer as a stopper. FIGS. 10A through 10D of the accompanying drawings illustrate how this method is put to actual use.
Referring firstly to FIG. 10A, an SiO.sub.2 film 62 is formed in an Si semiconductor substrate 1 and thereafter a lower wiring layer 63 is formed on the SiO.sub.2 film 62.
Then, as shown in FIG. 10B, a silicon nitride film 64 is formed as a stopper layer on the lower wiring layer 63 by deposition and subsequently another SiO.sub.2 film 65 is formed on the silicon nitride film 64 also by deposition as shown in FIG. 10C. Thereafter, the SiO.sub.2 film 65 is partly removed by polishing as shown in FIG. 10D.
However, as FIG. 10D suggests, the effect of the polishing operation varies depending on the position on the surface of the Si substrate 51. While there are areas where the silicon nitride film 64 operate effectively as a stopper layer against the polishing operation, it is totally removed and the lower wiring layer 63 is polished to a certain extent in some other areas on the Si substrate 1.
FIGS. 11A through 11C and FIGS. 12A through 12E of the accompanying drawings respectively illustrates two different known processes for preparing a thin film semiconductor device, where a silicon substrate is thinned by polishing.
Referring firstly to FIG. 11A, an SiO.sub.2 film 72 is formed in an Si substrate 71.
Then, as shown in FIG. 11B, another Si substrate 73 is applied to the Si substrate 71 with the SiO.sub.2 film 72 interposed therebetween and subsequently the Si substrate 73 is thinned by polishing as illustrated in FIG. 1C.
Consequently, as FIG. 11C clearly shows, the thickness of the silicon thin film 73 varies greatly depending on the position of the Si substrate and is totally removed in some areas.
A conceivable method of controlling the extent of polishing the silicon thin film 73 is to form an additional layer of SiO.sub.2 film, for instance, and use the layer as a stopper. FIGS. 12A through 12E of the accompanying drawings illustrate how this method is put to actual use.
Referring firstly to FIG. 12A, an SiO.sub.2 film 82 is formed in an Si substrate 81.
Then, as shown in FIG. 12B, another Si substrate 83 is applied to the Si substrate 81 with the SiO.sub.2 film 82 interposed therebetween. Subsequently, openings are formed in the Si substrate 83 until the openings reach the surface of the SiO.sub.2 film 82 as illustrated in FIG. 12C. Thereafter, as shown in FIG. 12D, another SiO.sub.2 film 84 is selectively formed in those openings to a desired thickness by deposition and then the Si substrate 83 is partly removed by polishing.
Here again, the effect of the polishing operation varies depending on the position on the Si substrate. While the polishing operation proceeds as far as somewhere in the middle of the SiO.sub.2 film 84 in some areas on the Si substrate, it is totally removed and along with the silicon thin film 83 in other areas.
Any known methods of manufacturing semiconductor devices involving steps of polishing the devices are accompanied by the above identified problems, which can be summarized as follows.
One of the most significant problems is that, with any known methods, the extent of polishing the device can hardly be controlled. Here, control of the extent of polishing the device means absolute control of the polishing rate and that of the evenness of the device surface. Any technology of manufacturing semiconductor devices will not and cannot be feasible for practical applications unless it is capable of controlling these two aspects. One known technique of controlling the extent of polishing is, as already described, to use a silicon nitride or SiO.sub.2 film as a stopper layer.
However, the use of a silicon nitride or SiO.sub.2 film as a stopper layer is not practical because they do not offer a sufficiently wide range of selectable ratios of the rate of polishing the proper object to that of polishing the stopper. Moreover, the range of selectable ratios of the rate of polishing the proper object to that of polishing the stopper varies greatly depending on the polishing slurry used in the polishing operation. For instance, the rate of polishing a SiO.sub.2 film will be very high if polishing slurry used for the polishing operation contains sodium hydroxide to a relatively large concentration. In other words, the material to be used for the stopper layer should be selected by considering the type of polishing slurry involved.
Thus, any conventional process of polishing semiconductor devices is accompanied by the problem of difficulty of controlling the extent of polishing the device and hence hardly feasible for practical applications.
It is also a common practice in any conventional process of polishing semiconductor devices that a test piece (specimen) of the product is polished to collect data for determining an optimum rate of polishing the device and then devices are polished at that determined optimum rate. However, the rate of polishing the device varies as a function of the time consumed for the polishing operation as typically illustrated in FIG. 13 and, therefore, the optimum polishing rate determined on the test piece does not necessarily reflect the actual polishing rate observed on the manufacturing line.
The manner in which the polishing rate changes with time is then greatly affected by the amount of polishing slurry held in the polishing cloth and the condition under which the polishing slurry is held in the polishing cloth. This influence of the amount of polishing slurry and the condition for the polishing of holding the slurry is so diverse that it is practically beyond control.
In an attempt to bring the rate of polishing the test piece closer to the actual rate of polishing devices on the manufacturing line, more than one and preferably a considerably large number of test pieces are used to determine an optimum polishing rate. Such a measure, however, entails an increase in the manufacturing cost due to a higher material cost for test pieces and a reduction in the operating hours of the manufacturing facilities, making it even more impractical.
Another proposed technique for accurately controlling the extent of polishing the device comprises preliminarily polishing the device to a relatively small extent, measuring the extent to which the device has been actually polished and then repeating the above procedures until the device is polished to a desired extent. While this method does not involve any increase in the material cost for the test piece, it is time consuming and significantly reduce the operating hours of the manufacturing facilities. Furthermore, in view of the fact that a semiconductor device is polished by merely 1 .mu.m in the manufacturing process, this method is by no means recommendable.
Thus, it should be stressed again that any known process of manufacturing semiconductor devices involving steps of polishing the devices is accompanied by the problem of difficulty of controlling the extent of polishing the device.
While there have been proposed techniques to overcome this problem including the one that uses test pieces to determine the rate of polishing the device and the one with which the device is polished in a plurality of steps and the extent to which the device has been polished is determined at each step, any of these techniques are not recommendable because they can not satisfactorily control the extent of polishing and involve an increase in the manufacturing cost.
There is also known a method of polishing and planarizing semiconductor devices as disclosed in U.S. Pat. No. 5,036,015 "Method of Endpoint Detection during Chemical/Mechanical Planarization of Semiconductor Wafers". According to this method, the turntable of a planarizing apparatus is driven to rotate by an electric motor and changes in the friction between the wafer held by a wafer holding device on the turntable and the polishing cloth for polishing the wafer are detected as changes in the electric current flowing through the electric motor.
For planarizing a silicon oxide film, a layer made of a material harder than the silicon oxide film is arranged under the silicon oxide film in advance and the planarizing operation is terminated when the polishing plane of the polishing cloth reaches the hard layer to increase the friction of the plane after completely removing the silicon oxide film by polishing.
This known technique is also not without problems as described below by referring to FIGS. 14 through 16.
FIG. 14 schematically illustrates a polishing apparatus of the above described type, which detects changes in the friction between the wafer 1 and the polishing cloth 504 held on the turntable 502 for polishing the wafer as changes in the electric currents respectively flowing through the electric motors 511 and 512 and displayed on the corresponding ampere-meters 513 and 514.
Referring now to FIG. 15, each of the electric currents flowing through the respective electric motors 511 or 512 varies as a quadratic function of the voltage of the corresponding power supply 515 or 516 and the reading for the current is affected by changes in the voltage. As seen from FIG. 16, however, since no load current Io flows through each of the electric motors when no load is applied thereto, it is difficult to accurately detect the level of friction taking place on the turntable.
Referring back to FIG. 14, the shafts 517 and 518 of the turntable and holding device of the polishing apparatus are connected to the respective shafts of the corresponding motors 511 and 512 by respective belts 519 and 520 in order to eliminate any adverse effects of pulsation of the motors to which the polishing plane of the polishing cloth may be subjected to. However, the belts 519 and 520 can slip around the respective shafts 511 and 512 while they are driven to run to change the loads of the motors 511 and 512 SO that the ampere-meters 513 and 514 may not correctly reflect the level of friction taking place on the turn table.
Meanwhile, according to another known method of polishing and planarizing a semiconductor device, the rate of polishing the device is determined from the number of rotations of the turntable per unit period of time and the load applied the polishing apparatus by the object of polishing in order to establish an optimum polishing time on the basis of the determined polishing rate and the required extent of polishing.
In a polishing apparatus designed to practice this method, a polishing cloth is arranged on a turntable which is driven to rotate by a drive motor and a holding device for holding an object of polishing is disposed on the polishing cloth. The holding device is also driven to rotate by another drive motor.
Then, a semiconductor wafer to be polished by this apparatus is put on the holder opposite to the turntable. The wafer comprises a wiring layer arranged on a silicon substrate with a first insulating film disposed therebetween and a second insulating film disposed on the first insulating film. The holder device and the turntable are driven to rotate for predetermined respective rotations per unit period of time by the respective drive motors and the polishing cloth which is rotating with the turntable is fed with a polishing slurry. Then, the holder device is moved down until the wafer comes to contact with the polishing cloth. Under this condition, a predetermined load is applied to the wafer and the holder device is moved horizontally along the surface of the turntable to polish the wafer for a predetermined period of time to planarize the surface of the second insulating film of the wafer that carries undulations thereon.
After the operation of planarizing the wafer is over, it is replaced by a new one and the above described procedures are repeated for each untreated wafer. When the polishing apparatus has been used for a predetermined service time, the polishing cloth is redressed to recover its original condition by using a brush. After experiencing a number of cycles of polishing and redressing, the polishing cloth is replaced by a new one.
According to the above described known polishing method, the rate of polishing the wafer is calculated from given polishing conditions or the rotations per unit period of time of the wafer holder device, that of the turntable and the load applied to the wafer and an optimum polishing time is selected from the polishing rate and the required extent of polishing. In other words, the polishing rate is assumed to be constant unless either or both of the polishing rate and the load are altered. In reality, however, the polishing rate changes as the level of friction between the wafer and the polishing cloth varies as a function of the time consumed for polishing the wafer even if the rotations per unit time and the load are not altered.
FIG. 17 of the accompanying drawings illustrate the relationship between the total service time of the polishing cloth and the polishing rate. The first 50 minutes in the total service time of the polishing cloth are defined as an initial stage, which moves into a working stage when the first 50 minutes have passed.
FIG. 17 shows that the polishing rate varies also with time in the working stage. This may be attributable to the changes in the surface condition of the polishing cloth that take place as the cloth is choked by particles of the polishing slurry and the cloth is worn out and by turn reduce the efficiency of feeding particles of the polishing slurry to and discharging them from the surface of the polishing cloth and hence the efficiency of polishing the wafer. More specifically, the surface of the polishing cloth 504 has a huge number of tissues suspended therefrom and pores separating them as illustrated in FIG. 18 and particles of the polishing are retained in those pores. Then, as the polishing cloth is pressed against the wafer, the particles of the polishing slurry retained in the pores are discharged onto the wafer. The efficiency of this polishing slurry feeding and discharging mechanism is reduced with time as the polishing cloth is worn out to vary the polishing rate with time. As the surface condition of the polishing cloth is further aggravated, it can give rise to scars on the polished surface of the wafer and degrade the planar condition of the polished surface.
A polishing cloth choked with particles of the polishing slurry can be redressed by means of a brush at an appropriate time. While the operation of redressing is an effective way of deterring the wear of the polishing cloth, the cloth requires replacement if its surface condition is not recovered by redressing as such a situation suggests that the service life of the cloth is over.
With the above described known polishing method, the timing or redressing the polishing cloth is selected on the basis of the experience of the operator and that of replacing the polishing cloth is determined on the basis of the polishing rate calculated from the measured value of the extent of polishing the wafer per unit period of time. This means that in most cases the polishing cloth is not timely redressed nor replaced and consequently the rate of polishing the wafer is not kept to a constant level nor accurately controlled.